Sliding Window Logic Simulation

Existing digital logic simulators typically depend on a discrete-time model of circuit behaviour. Whilst this approach is sufficient in many cases for the validation of the behaviour of synchronous circuits, it is not good at identifying glitches that are narrower than the available time resolution. Moreover, it is not generally feasible to accommodate uncertainty in delay time in such a way as to detect at an early design stage glitches that only occur under worst-case layout-specific or environment dependent timing conditions. This paper presents a technique, based upon abstract interpretation, that, given any synchronous or asynchronous circuit, allows possible glitches to be detected within a particular time window given known starting conditions. Since the underlying model is based upon dense (continuous) time, all possible glitches are detected regardless of how narrow they may be. Adopting a window length equivalent to the worst-case uncertainty in delay, then ‘sliding’ the window in time such that each successive window overlaps the previous window allows all possible glitches to be identified, without a need for exact timing information. Using this algorithm, it is possible to construct a logic simulator that is capable of automatically detecting possible glitches early in the design life cycle, before layout-specific timing parameters can be determined.